Pulse stuffing synchronization is a technique that is used to maintain clock synchronization in digital data communication systems by selectively inserting pulses into a digital data frame. As described in an article by D. L. Duttweiler, entitled: "Waiting Time Jitter," Bell System Technical Journal, January 1972, pp. 165-207, the data clock produced at the output of a pulse-stuffing synchronizer pair contains low frequency jitter, termed waiting time jitter, that cannot be removed. Since this jitter occurs at an arbitrarily low frequency, determined by the relative frequencies of clock signals involved, and is often time varying, it cannot be removed using standard filtering techniques, such as a phase locked loop.
An article by Yoshihisa Matsurra, et al, entitled: "Jitter Characteristics of Pulse Stuffing Synchronization," IEEE ICC Conference Proceedings, June 1968, pp. 259-264, and in an article by Seiichiro Kozuka, entitled: "Phase Controlled Oscillator for Pulse Stuffing Synchronization System," Review of the Electrical Communication Laboratory, Vol. 17, No. 5, May-June 1969, pp. 376-387, describe that when the pulse stuffing ratio is near a fractional ratio having a small denominator, the resulting jitter will be that having the largest amplitude. In particular, when the pulse stuffing ratio is near a ratio of q/p stuffs per stuffing opportunity, the low frequency component of the jitter has an amplitude of 1/p times the size of the stuffing pulse. As an example, if the stuffing ratio is near 1/2 stuffs per stuffing opportunity, the jitter has a peak-to-peak amplitude of 1/2 of the size of the stuffing pulse.
Because large amplitude jitter can pose problems in communication systems, limits are placed on the maximum jitter amplitude allowed. Such limits often split the jitter into two types--low and high frequency jitter; the high-frequency jitter is referred to as simply `jitter`, and the low frequency jitter, which has a frequency of less than 10 Hz, is referred to as `wander`.
One example of digital communication signals for which jitter and wander limits have been defined or standardized in various documents are DS1 (1.544 Mb/s) signals. The ITU-T (CCITT) Recommendation G.824 specifies the maximum allowable jitter for a DS1 signal. ANSI T1,403-1989 limits the maximum peak-to-peak wander and jitter in a 15 minute interval at 5 unit intervals (UI). In addition to these limits, the ANSI T1.101-1993 specification limits the wander of DS1 signals that are used to pass timing information. These limits are in terms of Maximum Time Interval Error (MTIE), and vary from 300 to 1000 ns over observation intervals of 1 to 1000 seconds.
One technique for transporting a DS1 signal over a twisted-pair wireline path is known as the High-bit-rate Digital Subscriber Line (HDSL). HDSL uses pulse-stuffing synchronization to convey the DS1 signal asynchronously to the signal transport mechanism (the synchronized signal), which is timed via a HDSL master oscillator. The stuffing pulses used in HDSL are approximately 5100 ns long, which is nearly 8 UI of the DS1 signal. The nominal stuffing ratio for HDSL is 1/2, so that the wander may be as large as 4 UI, which is approximately 2550 ns.
FIG. 1 diagrammatically illustrates an example of a sync-multiplexer arrangement for HDSL applications based upon the signal processing mechanism described in the above-referenced Duttweiler article. As shown therein, an unsynchronized data signal is coupled over an input link 11 to both a timing extractor 13 and an elastic store (buffer) 15. Timing extractor 13 is operative to generate a frame sync signal on line 17, when the data signal is framed and it is desired to keep a prescribed phase relationship between the framing of the data signal and the stuffing frame of an output data signal on a downstream output link 19. If a frame sync signal on line 17 is used, elastic store 15 is a frame aligned elastic store. The timing extractor 13 also extracts a write clock signal on write clock line 18. The write clock signal on write clock line 18 is employed to write the data signal on link 11 into elastic store 15, and is also applied as first input 21 of a phase comparator 23.
A synchronized data signal on data output line 25 from elastic store 15 is read out using a read clock supplied over read clock line 27 from an output multiplexer 30. The read clock is also applied to a second input 22 of phase comparator 23. Phase comparator 23 provides a binary output signal on line 31 to a control (combinational and sequential) logic circuit 33. Control logic circuit 33 responds to the logical states of its various inputs and supplies a control signal over line 39 to multiplexer 30.
In response to the control signal on line 39, multiplexer 30 is operative to switch output line 19 to one of the synchronized data signal on line 25, an `other` data signal on line 41, and a stuffing pulse data signal on line 43. Multiplexer 30 also switches the synchronized clock signal on line 35 to respective read clock lines 27, 42 and 44, in order to read the selected data signal. The `other` data signal on line 41 is derived from associated memory 40, which is customarily employed to store synchronization, maintenance, monitoring, and other various data that is incorporated into the output synchronized data signal. The stuffing pulse signal on line 43 is derived from associated memory 45 that stores the values of the stuffing pulses. Control logic circuit 33 directs multiplexer 30 to switch between the synchronized data signal on line 25 and the `other` data signal on line 41, in accordance with a predefined stuffing frame format. The predefined stuffing frame has an opportunity to have a predetermined number of stuffing pulses inserted every stuffing frame, based on the sampled value of the phase comparator output on line 31.